VHDL language programming error, seek advice

Great God

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library ieee;
use ieee.std_logic.all;
use ieee.std_logic_unsigned.all;

entity bisou is
port (a: in std_logic;
reset: in std_logic;
h1: out std_logic);
end bisou;
architecture bisou1 of bisou is
begin
u1: process (a)
begin
if (a'event and a = '1 ') then
h1 <= '1 ';
end if;
end process u1;
u2: process (reset)
begin
if (reset = '1 ') then
h1 <= '0 ';
end if;
end process u2;
end bisou1; - u1 end





library ieee; - u2 start
use ieee.std_logic.all;
use ieee.std_logic_unsigned.all;

entity bisou2 is
port (clk: in std_logic;
h2: in std_logic;
fre: out std_logic;
reset2: buffer std_logic);
end bisou2;
architecture bisou2 of bisou2 is
SIGNAL cnt1: std_logic_vector (10 DOWNTO 0); - shu chu gei bell
SIGNAL cnt2: std_logic_vector (21 DOWNTO 0); - yan shi 2s hou reset = 0
signal fr_low: std_logic;
signal fr_high: std_logic;
begin
fre <= fr_low;
reset2 <= fr_high;
u2: process (h2, clk)
begin
if h2 = '0 'then cnt1 <= "00000000000";
elsif (clk'event and clk = 1) then
if cnt1 = "11111111111" then cnt1 <= "00000000000";
else cnt1 = cnt1 + '1 ';
end if;
end if;
end process u2;

u3: process (h2, clk)
begin
if h2 = '0 'then cnt2 <= "0000000000000000000000";
elsif (clk'event and clk = '1 ') then
if cnt2 = "1111111111111111111111" then cnt2 <= "0000000000000000000000";
else cnt2 = cnt2 + '1 ';
end if;
end if;
end process u3;

u4: process (cnt1)
begin
if cnt1 = "11111111111" then fr_low <= not fr_low;
end if;
end process u4;

u5: process (cnt2, cnt1)
begin
if cnt2 = "1111111111111111111111" then
fre_high <= '1 ';
cnt2 <= "0000000000000000000000";
cnt1 <= "00000000000";
else fre_high <= '0 ';
end if;
end process u5;
end bisou2; - u2 end

library ieee; - u2 + u1 start
use ieee.std_logic.all;
use ieee.std_logic_unsigned.all;

entity bisou3 is
port (a: in std_logic;
b: in std_logic;
clk: in std_logic;
fre_low: out std_logic;
buff: buffer std_logic);
end bisou3;
architecture bisou3 of bisou3 is
signal tem1, temp2: std_logic;
component bisou
port (a1: in std_logic;
reset: in std_logic;
h1: out std_logic);
end component;

component bisou2
port (clk: in std_logic;
h2: in std_logic;
fre: out std_logic
reset2: buffer std_logic);
end component;
begin
u0: bisou port map (a1, temp2, temp1);
u1: bisou2 port map (clk, temp1, fre_low, temp2);
end bisou3;

Pin Description : The system functions to detect the first entity bisou input disciplining a, a once rising edge on the output h1 is high, which is reset to the first entity bisou reset pin , reset to 1:00 , will h1 low. . . . The second entity has a clock input pin bisou2 clk, another h2 ( in fact the third entity , the connection achieved h1 and h2 ) when h2 is high, the count is started, the output frequency is constant fre pin another high reset2 output frequency counting when it reaches the maximum count , which is 1 , because the implementation of the reset signal reset reset2 connection with the first entity , the feedback control so that it can h1.. . .

procedural error four places , seeking the guidance of the great God ?
------ Solution ---------------------------------------- ----
begin under two processes , and the two signals on the same sensitive processes , which causes the system to assign the two errors . . . There are many questions , writing is not standardized
For example, use ieee.std_logic.all should use ieee.std_logic_1164.all